Xputer-related Publications pt. 1 (new version):
Part 2
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Old version
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Reiner's Publications -
Reiner's homepage
Paragraph numbering ruined ? Use another browser !
(m. P. Braun, E. Ewald, J. Hassdenteufel, R.
Hauck, A. Hirschbiel, M. Weber): Das DRC-KL-Programm- system; CSG, Fachbereich Informatik; Univ. Kaiserslautern,
1983 (engl.: "DRC-KL-Program-System")
(r) (w. P. Braun, J. Hassdenteufel: Pixel-oriented
Layout Analysis: Semi-Automatic Analyzer Generation for Design Rule Check
and Circuit Extraction; report, Univ. Kaiserslautern, 1983
(r)(w. R. Hauck, A. Hirschbiel, W. Nebel, M. Weber):
PISA, a CAD package and special hardware for pixel-oriented layout analysis; Report,
Univ. Kaiserslautern, 1984
-- citation
at Buffalo
(r) (w. R.Hauck, A.Hirschbiel, W.Nebel, M.Weber):
PISA - A CAD package and special hardware for pixel-oriented layout analysis, ICCAD, Santa Clara,
1984, IEEE, New York 1984 -- citation
<pdf>
(r) (w. J.Bloedel, R.Hauck, M.Ryba, H.Salzmann, M.Weber): PISA user manual;
report, Kaiserslautern 1985
(b) Toward Engineering System Sciences;
SEFI Annual Symposium, Madrid, September 1985
(g) (m. K.Bastian, W.Nebel): VLSI-Algorithmen: innovative Schaltungstechnik statt Software - SHUFFLE SORT: VLSI-Beispiel eines Sortierers; G.. f. Meß- und
Regelungstechnik: Tagg. Mikro- elektronik i.d. Automatisierungstechnik, Baden-Baden
'85; VDI-Ber. 550, Düsseldorf'85 -
xlate title
<pdf>
(ti) Map-oriented Processing: Akzelerations-Konzept und VLSI-Entwicklungsumgebung für eine Klasse von Datenverarbeitungssystemen;
Seminar des IMS, Duisburg, Juli 1986
(g) (w. A.Hirschbiel, M. Weber): MOM - Map Oriented Machine, Proc. Int'l Workshop on Hardware Accelerators, Oxford, UK Oct.
1987; in T. Ambler, P. Agraval, W. Moore (eds.): Hardware
Accelerators for Electrical CAD, Adam Hilger 1988
<PDF>
<PDF>
<ppt>
<photos>
citation at
Buffalo
(g) (w. A.Hirschbiel, M.Weber): MOM - Map Oriented Machine, International Conference on Parallel Processing and Applications,L'Aquila, Italy, Sept. 1987.
<PDF>
<photos>
(g) (w. A.Hirschbiel, M.Weber): A Flexible Architecture for Image Processing; Proceedings of the EUROMICRO Symposium, Portsmouth, UK, 1987.
<PDF> <pdf-2>
<pdf-3>
(r) Entwurf eines Universalprozessors mit Hocharchitektur, Kaiserslautern, 1986 -
xlate title -
(r): Seminar "Innovative Prozessor-Architekturen"; Winter-Semester 1987/88, Fachbereich Informatik, Technische Universität Kaiserslautern
<PDF_T_1>
<PDF_T_2>
<PDF_T_3>
(r) (w. A.Hirschbiel, M.Weber):
MOM - Map Oriented Machine - An Innovative Computing Architecture;
Bericht Nr. 181 / 88, Fachbereich Informatik,
Universität Kaiserslautern, 1987
<PDF>
<photos>
(g) (w. A.Hirschbiel, M.Weber): MOM - Map oriented Machine; in: E.Chiricozzi & A.D'Amico : Parallel Processing and Applications, North-Holland,
Amsterdam / New York, 1988
<PDF> <photos>
(g) (w. A.Hirschbiel, M.Weber): MOM - Map oriented Machine; in: Ambler,
Agrawal, Moore: Hardware Accelerators, Adam Hilger, 1988
<PDF> <photos>
<pdf-2>
/g) R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; Conference on Parallel Processing and Applications,
L'Aquila, Italien, 1987
<PDF> <pdf-2>
<photos>
(g) (w. M.Ryba): Partitionierungsschemata für Rechnerstrukturen; in: Valk (ed.) : Proc 18. GI-Jahrestagung, Springer-Verlag, Berlin
/ Heidelberg / New York, 1988 -
translation of title -
(g) (w. A.Hirschbiel, M.Weber): Mapping Systolic Arrays onto the Map-Oriented
Machine (MoM); Int'l Worksh on Systolic Arrays, May 1989, Killarney, Ireland <PDF>
<photos>
(g) (w. A.Hirschbiel, M.Weber): MOM - a partly custom-design architecture
compared to standard hardware; IEEE Compeuro, May '89, Hamburg Germany'89 <photos> <PDF>
(g) (w. K. Lemmert): SYS3 - A CHDL-Based Systolic
Synthesis System; Int'l Conference on Computer Hardware Description Languages (CHDL'89),
June 1989
Washington, D.C., U.S.A.
(g) (w. K. Lemmert, M. Riedmüller): Synthesis of Systolic Architectures
Using the SYS3-System;
EUROMICRO Symp, Sep 1989, Cologne, Germany, Elsevier
Science Publishers, 1989
(b) Der Rechner aus dem Elfenbeinturm; Markt & Technik, 44, Oct 1989. -
translation of title -
(N) SYS3: was ist neu? - Notiz, 1989
<PDF>
(g) (w. A.Hirschbiel, M.Weber): A Pseudo Parallel Architecture for Systolic Algorithms.
Proc. of the International Conference on VLSI and CAD, 17-20 Oct 1989, Seoul, Korea
<PDF>
(b) Xputer: Rechner nach neuartigen Prinzipien; GI Informatik Spektrum, Dec 1989, Springer-V., Berlin / Heidelberg / New York
1989 xlate title
<PDF>
<inforapid>
<freenet>
(g) (w. A.Ast, A.Hirschbiel, M.Riedmüller, K.Schmidt, M.Weber):
Using Xputers as Inexpensive Universal Accelerators in
Digital Signal Processing; Bilkent'90 In'l Conf on New Trends in Com- munication, Control
& Signal Processing; 1990, Ankara, Turkey,
<PDF>
<inforapid>
<freenet>
(f) (folder): Xputers - A New Machine Paradigm -
A NEW R&D Area --- Industrial Competitiveness by drastically more performance on much less hardware.
1990, Bruchsal, Germany
<PDF>
(r) Xputers: a new R&D area; report, Fachb. Informatik,
TU
Kaiserslautern, 1990
<PDF>
(m) Xputers - A New Machine Pardigm - A New R&D Area; group flyer, Kaisersl. 1990;
<pdf>
(g) (w.A. Hirschbiel, M.Weber): Xputers - An Open Family of Non von
Neumann Architectures; Proceedings 11th ITG/GI-Conferenz Architektur von Rechensystemen, March 1990, Munich, Germany, VDE-Verlag 1990.
<PDF>
<PDF>
also see
Christophe Bobda
(s) (w. A. Hirschbiel, M.Weber): Non-von-Neumann: Is the Technology Transfer an Achievable Goal ?
subm. to ITG/GI-Konferenz Architektur von Rechensystemen, March 1990, Munich, Germany
(for final version due to reviewing process see above under Compeuro)
<PDF>
<inforapid>
<freenet>
(g) (w. A.Hirschbiel, M.Weber): The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration;
International Workshop on Algorithms and Parallel VLSI Architectures, Pont-à-Mousson, France, June 1990
<PDF>
(k) (invited presentation)
Xputer -
Novel High Performance Computers: Principles and Implemenation; IBM Research
Laboratories, Boeblingen, Germany June 21, 1990
(g) CASHE using a new Machine Paradigm; The 2nd IFIP International Workshop on Hardware/Software Codesign (Codes/CASHE’93),
May 24 – 27, 1993, Innsbruck, Austria.
<PDF>
(g) (w. A.Hirschbiel, M.Weber): Using Xputers as Universal Accelerators for Neuro Network Simulation and its Applications; Int'l
Neural Netw. Conf., INNC 90, Paris, France, Juli 1990.
<PDF>
(g) (w. A.Hirschbiel, M.Weber): The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; 1990 International
Conference on Parallel Processing,August 1990, St. Charles, Illinois, USA,
<PDF>
<PDF2>
<inforapid>
<freenet>
(g) (w. A.Hirschbiel, M.Weber): A Novel Paradigm of Parallel Computation
and its Use to Implement Simple High Performance Hardware; CONPAR/ VAPP
IV, Sep 1990, Zürich, Switzerland
<PDF>
xx!
(g) (w. A.Hirschbiel, K. Schmidt, M.Weber): A Novel ASIC Design Approach
based on a New Machine Paradigm; European Solid-State Circuits Conf.
'90, Sep 90, Grenoble, France,
<pdf>
<pdf>
Invited Reprint:
in IEEE-JSCC - Journal of Solid State Circuits Systems, July 1991
(g) (DM 1000,-- Best Paper Award)
(w. A.Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber):
Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image
Preprocessing; 12. DAGM-Symp. Mustererkennung, Sep 1990, Oberkochen-Aalen,
<award>
<pdf>
<more awards>
(g) (w. A.Hirschbiel, K.Lemmert, M. Riedmüller, K. Schmidt, M.Weber:) Xputer Use in Image Processing and Digital Signal Processing;
SPIE Visual Communication and Image Proc'90, Lausanne, Schweiz, Oct 1990.
(g) (w. A.Hirschbiel, M.Weber): Xputers: Very High Throughput by Innovative Computing Principles; 5th Conf. on Information
Technology (JCIT), Jerusalem, Israel, Oct 1990, IEEE CS Press, 1990.
(g) (w. A. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber):
A Flexible Hardware Accelerator and its Applications in EDA; The 16th CAVE Workshop in Ghent, Belgium, Dezember 1990
(N) (w. A.st, H. Reinig, M. Riedmüller, K. Schmidt) Übersicht über die Hard- und Softwarearbeiten für die MoM3; TU Kaiserslautern, 1991
<pdf>
(r) (w. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance
Hardware; Univ. Kaiserslautern, Informatik, 1990
<PDF>
(bj) (w. A.G. Hirschbiel, M.Weber): Rekonfigurierbare ALU erlaubt Parallelisierung
auf unterster Ebene; VMEbus, Februar 1990.
translation of title
(g) Xputer: ein neues Maschinen-Paradigma für Höchstleistungsrechner;
Lessacher Informatik-Kolloq, Lessach, Austria, Sep 1990, Springer-Verlag 1991
-
translation of title -
<inforapid>
<freenet>
(r) (w. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber):
Xputers: a High performance Machine Paradigm - Hardware Principles, Programming, Compilation Techniques;
in: K. Ecker, R. Hirschberg (editors): "Workshop über
Parallelverarbeitung, Lessach, Austria, 17. - 21. September 1990"
<PDF>
(g) (w. A.G. Hirschbiel, M.Weber):
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware;
InfoJapan'90 - memorating 30th Anniversary Computer Society of Japan, Tokyo, Japan, 1990,
Invited Reprint:
in Future Generation Computer Systems 7 91/92, North Holland
<PDF>
(kj) (invited reprint)
(w. A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A Novel ASIC Design Approach Based on a New Machine Paradigm;
IEEE-JSSC - Journal of Solid State Circuits, July 1991
<PDF>
(gj) (w. K. Schmidt, H. Reinig, M. Weber): A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; in Will Moore,
Wayne Luk (ed.): Field Programmable Logic and Applications, Abingdon
EE&CS Books, Abingdon, 1991
<PDF>
A. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber): A
High Performance Machine Paradigm Based on Auto-Sequencing Data Memory;
HICSS - 24th Hawaii Int'l Conference on System Sciences,
Koloa Hawaii, January 1991
<PDF>
<award>
<PDF-2>
<pdf-3>
<pdf-4>
(g) (w. H. Reinig, M. Riedmüller, K. Schmidt): A Novel Computational
Paradigm: Much More Efficient Than Von Neumann Principles; The 13th IMACS World
Congress, Dublin Ireland, July 1991
<PDF>
(g) (w. K. Schmidt, H. Reinig, M. Weber): A Novel Compilation Technique
for a Machine Paradigm Based on Field-Programmable Logic;
Conf. on Field Programmable Logic and Applications, Oxford 1991
<PDF>
Karin Schmidt: puter - eine Alternative zum puter ? UNI SPECTRUM, Technische Universität Kaiserslautern, 1990
<pdf>
|
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(r) (m. A.Hirschbiel, M.Riedmüller, K.Schmid, M.Weber:)
Xputers: A New R&D Area; Kaiserslautern, 1991
(r) (w. J. Blödel, D. Schröder, W. Wilkes): DASSY -
Übersicht über die Informationsmodelle; Bericht zum Meilensteintreffen M3; DASSY Projekt; 23. Juli 1991 -
translation of title -
(r) (w. M. Riedmüller, K. Schmitt, M. Weber): A Novel Asic Design Approach Basd on a New Machine Paradigm; Interner Bericht 212/91,
Universität Kaiserslautern, Fachbereich Informatik, Juli 1991
(bj) (w. A. Ast, et al.): High Performance VLSI Signal Processing; in (Hrsg: M. Bayoumi): VLSI Image and Signal Processing;
Kluwer Akademic Publishers, Boston, 1992.
(i) (n. e. Interview d. Klaus Schlüter) Xputer - Innovation für den Multimedia-Markt; Funkschau 5/1992
<pdf>
(g) (w. A. Ast, H. Reinig, K. Schmidt, M. Weber): A Novel High-performance Machine Paradigm and ASIC Design Methodology; Int'l Design Automation Worksh, June. 92, Moskau,
<PDF>
<PDF>
(bj) (w. A. Hirschbiel,K. Schmidt,M. Weber): A Novel Paradigm of Parallel
Computation and its Use to Implement Simple High-Performance Hardware, inside Future Generation Computer Systems 7 91/92, North Holland: an
Invited reprint of InfoJapan'90- , Tokyo, Japan, 1990
<PDF>
(g) (w. A. Ast, et al.): Ein neuartiger Ko-Prozessor zur Akzeleration von Algorithmen mit regelmäßigen Datenabhängigkeiten,
GI/ITG Workshop Hochintegrierte Schaltungen für Parallelarchitekturen, 2. - 3.7.92, Irsee, Germany, 1992 -
xlate title
(g) (w. H. Reinig): Der GAG-Adreßgenerator und seine Anwendung als Akzelerator,
GI/ITG Worksh. Hochintegrierte Schaltungen f. Parallelarchitekturen, July 1992, Irsee, Germany,
xlate title
<pdf>
<pdf2>
<pdf3>
(B) (
Book Editor w. H.
Gruenbacher): "
Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping;
2nd Int'l Conference on Field-Programmable Logic
and Applications, Vienna, Austria, August/September 1992"; Lecture Notes in Computer Science (LNCS No. 705), Springer-Verlag 1993
- ISBN 3-540-57091-8
<Reiner's books>
<the conference>
(g) (w. A. Ast, R. Kress, H. Reinig, and K. Schmidt): Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic ;
2nd Int'l Workshop on Field-Programmable Logic and Applications,
August 31 - September 02, 1992, Vienna University of Technology, Vienna, Austria, 1992, <PDF>
(ti) Xputer: ein Neues Maschinen-Paradigma; Kolloq. Univ. Augsburg, Feb'93
<PDF> <PDF>
(g) (w. H. Reinig, M. Weber): Design of an Address Generator, The 3rd Eurochip
Workshop on VLSI Design Training, 30.9 - 2.10.92, Grenoble, France,
1992
<PDF>
<pdf2>
(ti) (invited
presentation): Xputer: ein neues Hochleistungs-Maschinenparadigma; Fa. Hermstedt, Mannheim, Germany, Oktober 1992
(s) Hardware/Software Co-Design; 3rd
Int'l Worksh
Field-Programmable Logic & Appl., Oxford UK Sep 1993
(g) (w. A. Ast, J. Becker, R. Kress, H. Reinig, and K. Schmidt): MoPL-3: A New High Level Xputer Programming Language; The 3rd International
Workshop on Field Programmable Logic & Appl., Oxford, UK, September 1993
<PDF>
<inforapid>
<freenet>
<home>
<JPG-zig-zag-scan-animation>
(g) (invited Paper)
Xputer: ASIC or Standard Circuit? GME Fachtagung
Mikroelektronik, Dresden, März 1993, VDE-Verlag
<PDF>-2 figs fehlen
(r) Xputer-related Literature;
Interner Bericht, Informatik, TU Kaiserslautern, 1993
<pdf>
<pdf2>
(m) Several Early Reconfigurable Computing Start-ups; memo, 1993,
<pdf>
(B) (
Book Editor w. M. Servít):
Field-Programmable Logic: Architectures, Synthesis, and Applications;
Lecture Notes in Computer Science, Springer-Verlag 1994.
<about this conference>
What means Reconfigurable Computing? See
Tibor Krajčovič, PhD.
<Reiner's books>
(bj) (w. A. Ast, H. Reinig, K. Schmidt, M. Weber): A General Purpose Xputer Architecture derived from DSP and Image Processing;
in M.A. Bayoumi (ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994.
(g) (w. R.Kress, H.Reinig): A Reconfigurable Data-diven ALU for Xputers;
IEEE Worksh on FPGAs for Custom Computing Machines, FCCM'94,
Napa, CA. 1994.
<PDF>
<inforapid>
<freenet>
(g) (w. R. Kress, H. Reinig): An FPGA Architecture for Word-Oriented Datapaths;
Canadian Workshop on Field-Programmable Devices, FPD'94, Kingston, Ontario,
June 13-16, 1994
<PDF>
(g) (w. R. Kress, H. Reinig): A Reconfigurable Arithmetic Datapath Architecture: GI/ITG-Worksh
"Architekturen für hochintegrierte Schaltungen", Schloß
Dagstuhl, Bericht 303, pp. 53-59, Juli
1994
<PDF>
(g) (w. R. Kress and H. Reinig): A New FPGA Architecture for Word-oriented Datapaths; The 4th International
Workshop on Field Programmable Logic and Applications,
FPL'94, Prague, Czechia, September 7-10, 1994, Springer-Verlag, 1994
<PDF>
(g) (w. A. Ast, J. Becker, R. Kress, H. Reinig, K. Schmidt): Data-procedural Languages for
FPL-based
Machines; 4th International Workshop on Field Programmable Logic and
Applications,
FPL'94, Prague, Czechia, September 7-10 1994, Springer Verlag
<pdf>
(r) Xputers and their relations to H/S Codesign; report, Kaiserslautern, Sep 1994
<PDF>
(f) (fragment): Xputers - and their relations
to H/S Codesign -. Sep 1994, Informatik, TU Kaiserslautern, Germany (first of 22 pages History of Xputers)
<gif>
(g) (w. K. Schmidt): Parallelizing Compilation for a Novel Data-Parallel Architecture;
in; J. P. Gray, F. Naghdy (eds.), PCAT-94, Parallel omputing: Technology and Practice, Wollongong, Australia,1994 <PDF>
(invited tutorial)
Xputers, a New
Computational Paradigm; Microelectronics
Inst. Singapore, Nov 1994
(g) (w. K. Schmidt): A Restructuring Compilation Method for the Xputer Paradigm:
IWPP 94, Proc. Int. Workshop on Parallel Processing, Bangalore, India, Dec. 1994
<PDF>
(g) (w. K. Schmidt): A Restructuring Compilation Method for the Xputer Paradigm:
J, Brasilian Computer Society; Special Issue on Electronic Design Automation, no.2, vol. 2, Nov 1995
<PDF>
(r) Hardware/Software Codesign; Internal Report No. 246/94, University of Kaiserslautern, 1994.
(bj) Algebraischer Entwurf regelmaessiger Schaltungen;
in: R. Hartenstein: Standort Deutschland: Wozu noch Mikrochips? Einfuehrrung in Methoden der Technischen Informatik; ITpress Verlag, 1994
pdf --
fm
(g) (w. K. Schmidt): Combining Structural and Procedural Programming by Parallelizing Compilation;
Proceedings of the Symposium on Applied Computing, Nashville, TN, Feb. 1995
<PDF>
(bj) (w. J. Becker, et al.): High-Performance Computing Using a Reconfigurable Accelerator;
CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1995
<PDF>
(bj) (w. J. Becker, et al.): A Novel Machine Paradigm to Accelerate Scientific
Computing; Computer Science & Informatics Journal, Special Issue of Scientific Computing, Computer Society of India, 1996
<PDF>
(k)
(handout and presentation of an invited full day
VLSI Design Course) R. Hartenstein (chair), J. Becker, R. Kress, W. Reinig:
Xputers: Principles, Architectures, Performance; Tutorial on Xputers; 4 day tutorial at LIRMM,
University of Montpellier, Montpellier, France, Sept. 1995
(gj) (w. J. Becker, et al.): A Novel Two-Level Hardware/Software Co-Design Framework; Journal of the Brazilian Computer Society, Special Issue on
Electronic Design Automation, Dec. 1995
<PDF>
(gj) Hardware/Software Co-Design; GI Informatik-Spektrum, 1995
- translation of title -
(gj) Custom Computing Machines; GI Informatik-Spektrum, 1995
<pdf>
(g) (w. K. Schmidt): A Restructuring Compilation Method for the Xputer Paradigm:
Journal of the Brasilian Computer Society; Special Issue on Electronic Design Automation, no.2, vol. 2, Nov 1995
<PDF>
(g) (w. J. Becker, et al.): CoDe-X: A Novel Two-Level Hardware/Software
Co-Design Framework; 9th International Conference on VLSI Design, Bangalore,
India, Jan. 1996
<PDF>
<PDF>
(g) (w. J. Becker, et al.): A Reconfigurable Parallel Architecture to Accelerate Scientific Computation;
International Conference on High Performance Computing, New Delhi, India, Dec. 1995
<pdf>
(g) (w. J. Becker, et al.): A Profiling-driven Hardware/Software Partitioning
of High-Level Language Specifications; Workshop on Logic and Architecture Synthesis, Grenoble, France, Dec. 1995
(k) (keynote address)
Custom Computing Machines - an overview;
Workshop on Design Methodologies for Microelectronics, DMM'95, Smolenice
Castle, Czechia, Sep 1995
<pdf>
<doc>
<keynotes>
(g) (w. J. Becker, et al.): A Two-Level Hardware/Software Co-Design Framework for Automatic Accelerator Generation; Workshop on Design Methodologies
for Microelectronics, DMM'95, Smolenice Castle, Czech Republic, pp. 145-152, Sept. 1995
<PDF>
<pdf-2>
(g) (w. H. Reinig):
Novel Sequencer Hardware for High-Speed Signal Processing; Workshop on Design Methodologies for Microelectronics, DMM'95, Smolenice
Castle, Czech Republic, Sept. 1995
<PDF>
(g) (w. H. Reinig, et al.): A Scalable, Parallel, and Reconfigurable Datapath Architecture; 6th Int'l Symp on IC Technology, Systems &
Applications, ISIC'95, Singapore, Sept. 1995
<PDF>
<pdf-2>
<pdf-3>
(g) (w. R. Kress): A Datapath Synthesis System for the Reconfigurable Datapath
Architecture; Asia and South Pacific Design Automation Conf., ASP-DAC'95,
Makuhari, Chiba, Japan, Aug./Sept. 1995
<PDF>
<PDF2>
(g) (w. J. Becker, et al.): A Parallelizing
Compilation Method for the Map-oriented Machine; Int'l Conf. on
Application-Specific Array Processors, ASAP'95, Strasbourg, France, IEEE CS
Pr., July 1995 <PDF>
(g) (w. J. Becker, et al.): High-Performance Computing Using a Reconfigurable
Accelerator; High Performance Computing Symposium, HPCS'95, Montreal, Canada, July 1995
<PDF>
<award>
(g) (w. H. Reinig, et al.): A Reconfigurable Accelerator for 32-bit Arithmetic;
Workshop on Reconfigurable Architectures, Santa Barbara, CA, April 1995
<PDF>
(b) (w. J. Becker, et al.): A Reconfigurable Machine for Applications in
Image and Video Compression; European Symposium on Advanced Networks and
Services: Conference on Compression Technologies and Standards for
Image and Video Compression, Amsterdam, The Netherlands, March 1995
<PDF>
(r) (w. A. Ast, J. Becker, et al.): Data-procedural Languages for FPL-based
Machines; Universität Kaiserslautern, Fachbereich Informatik, Interner
Bericht, Nr. 264/95, 1995
<PDF>
(k) (w.J. Becker, R. Kress, H. Reinig:) A Novel Hardware/Software
Co-Design Framework; Journal of the Brasilian Computer Society: Special Issue
on Electronic Design Automation, no.2, vol. 2, pp.16-26, Nov 1995
<PDF>
(g) (w.
J. Becker, et al.)
A Profiling-Driven Hardware/Software Partitioning
of High Level Language Specification; IFIP Int'l Workshop on Logic
and Architecture Synthesis, Grenoble, France, 18. - 19. Dec 1995
<PDF>
(w) (w. J. Becker, A.Hirschbiel, R. Kress, H. Reinig, M. Riedmüller, K. Schmidt, M.Weber): FQA about Xputers; Fachbereich Informatik, TU Kaiserslautern, 1966
<htm>
(g) (w. J. Becker, et al.) Two-Level Hardware/Software Partitioning
Using CoDe-X; IEEE Int'l Workshop on Computer Based System Engineering
(CBSE'96), Friedrichshafen, Germany, March 1996
<PDF>
(g) (w. J. Becker, et al.) Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine;
ACM/IEEE International Workshop on Hardware/ Software Co-Design Codes/CASHE/CODES'96, Pittsburgh, PA, USA, March 18 - 20, 1996
<PDF>
(g) (w. J. Becker, M. Herz, R. Kress, U. Nageldinger:) A
Partitioning Programming Environment for a Novel Parallel Architecture;
The IEEE Internationl Parallel Processing Symposium (IPPS'96), Honolulu, Hawaii, USA,
15-19 April 1996
<PDF>
<pdf2>
(b) (w. J. Becker, M. Herz, et al.) A Parallelizing Programming Environment
for Embeded Xputer-based Accelerators; High Performance Computing Symp, HPCS'96, Ottawa, Canada, June 1996
<PDF>
<pdf2>
(B) Null Bock auf High Tech; Arbeitsplatz-Export: nur wegen zu hoher Löhne?;
IT Press, 1996 - ISB N 3-9
(g) (w. R. Kress) An Architecture for Highly Parallel Computer Arithmetic; The 2nd International Conference on Highly Parallel Computing Systems
(MPCS'96), Ischia, Italy, May 6 - 9, 1996
(g) (w. J. Becker, et al.) Application-specific Microprocessor Design Methodologies:
General Model vs. Tinkertoy Approach; GI / ITG Workshop on Custom Computing,
Dagstuhl, Germany, 19-21 June 1996
<PDF>
(b) (invited paper): High-Performance Computing": über Szenen
und Krisen; GI / ITG Worksh on Custom Computing, Schloß
Dagstuhl, Wadern, Germany, 19 - 21 June 1996
translation of title
<PDF>
(it) (Invited Tutorial, together with
Jürgen Becker): Xputers and Their Programming Environment; ARM
Advanced RISC Machines, Ltd. Europe, Cambridge, UK, July 24, 1996.
(g) (w. J.Becker, M.Herz, et al.); A Synthesis System for
Bus-based Wavefront Array Architectures; ASAP'96 Int'l Conference on Application-Specific Systems, Architectures and Processors, Chicago, Ill,
USA, Aug 19-21, 1996
<PDF>
<pdf2>
(g) (w. J.Becker, et al.): Custom Computing Machines vs.
Hardware/Software Co-Design: from a globalized Point of View;
The 6th International
Workshop on
Field Programmable Logic and Applications (FPL'96);
Darmstadt, Germany, September 23-25, 1996
<PDF>
(B) (
Book Editor
w. M. Glesner):
Field-Programmable Logic; Lecture Notes in Computer Science, Springer-Verlag
Berlin/Heidelberg/New York, 1996.
<the conference>
<Reiner's books>
(b) (w. J. Becker, M. Herz, et al.): Co-Design and High Performance Computing:
Scenes and Crisis; Proc. Reconfigurable Technology for Rapid Product Development
& Computing - Part of SPIE's Int'l Symposium VOICE, VIDEO and DATA
COMMUNICATIONS, PHOTONICS EAST, Boston, USA, Nov 1996
<PDF>
(bj) (w. J. Becker, et al.): A Novel Machine Paradigm to Accelerate
Scientific Computing; Computer Science and Informatics Journal: Special
issue on Scientific Computing, Computer Society of
India, 1996
<pdf>
<pdf-2>
(g) (w. J. Becker, et al.): An Embedded Accelerator for Real Time Image
Processing; 8th EUROMICRO Workshop on Real Time Systems, L'Aquila, Italy,
June 1996
<PDF>
(N) SYS3: Mapping Systolic Arrays onto Xputers; DRAFT book chapter; 1996
<PDF>
(N) Application Areas for Xputers; DRAFT book chapter; July 1996
<PDF>
(g) (w. J.Becker, M.Herz, U.Nageldinger): A General Approach in System
Design Integrating Reconfigurable Accelerators; Proceedings of the IEEE 1966 International Conference on Innovative Systems in Silicon (ISIS); Austin, Texas, USA,
October 1996
<PDF>
(g) (w. J. Becker): Hardware/Software Co-Design for data-driven
Xputer-based Accelerators; Proceedings of the 10th International Conference on VLSI Design (Theme: VLSI in Multimedia Applications), January 4-7, 1997, Hyderabad, India
<award>
<Xputer Software 1997>
<pdf>
(g) (w. J. Becker): A Two-level Co-Design Framework for data-driven Xputer-based
Accelerators; Proceedings 30th Hawaii International Conference on System Sciences (HICSS-30),
January 7 - 10, 1997, Wailea, Maui, Hawaii, USA,
<Presse-Echo>
<inforapid>
<freenet>
<pdf>
(g) (w. J. Becker): Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators;
The 5th International Workshop on
Hardware/Software Co-Design (CODES/CASHE'97), Braunschweig, Germany, March
24 - 26, 1997
<PDF>
(g) (w. J. Becker, K. Schmidt): Performance Evaluation in Xputer-based Accelerators;
Proceedings of the 4th Reconfigurable Architectures Workshop (RAW-97), in
conjunction with the 11th International Parallel Processing Symposium, IPPS'97, Geneva, Switzerland, April 1-5,1997
<PDF>
<RC 1997-2000>
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